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本文为英国帝国理工学院（作者：TERRENCE SUI-TUNG MAK）的博士论文，共201页。
在超大规模集成电路（VLSI）设计中，片上通信系统已成为一个非常重要的课题，因为技术集成化的趋势更倾向于逻辑而不是互连。互连通常决定系统性能，因此，必须研究新的方法和系统架构，以便跨芯片提供高性能通信服务。现场可编程门阵列（FPGA）作为一种可以在制造后对硬件进行编程的ASIC，其互连挑战更加严峻。由于互连扩展，FPGA之间的通信将恶化。可编程结构、交换机和特定的路由体系结构也引入了额外的延迟和带宽降低，进一步阻碍了芯片内的通信性能。以往的研究主要集中在优化FPGA中的逻辑元件和功能单元上。与可编程互连的通信很少受到关注，也没有得到充分的理解。
本论文是最早研究建立在可编程结构之上的片上通信系统的论文之一，并提出了最大化互连吞吐量性能的方法。本文的主要贡献有三个方面：（i）分析了可重构结构中由于路由拥塞而导致的片上互连边缘效应对通信信道带宽的影响；（ii）通过利用可重构互连结构的基本电气特性显著提高互连吞吐量的新模拟波信令方案，这种新方案可以潜在地缓解互连扩展的挑战。（iii）在片上网络（NoC）系统中提供自适应路由的新型动态规划（DP）网络。DP网络结构对路由规划和动态路由进行运行时优化，有效地利用了硅内带宽。本文探索了可重构系统设计的一个新领域，提出了新的方法和概念来提高FPGA上的通信吞吐量性能，这在新技术过程中至关重要。
On-chip communication system has emerged as a prominently important subject in Very-LargeScale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes.
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引言
- 项目背景
- 边缘互连与通信链路中的带宽退化
- FPGA中的波流水线芯片内信令
- 用于片上动态路由的DP网络
- 结论与展望 附录A 互连长度的简单近似 附录B 长互连的功率消耗 附录C 波流水的互连测试 附录D 最大化吞吐量的互连设计
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